AML-07 FPGA Architecture for AI Acceleration - Enroll Now This course develops systematic and detailed understanding of the Altera® FPGA device family and the Quartus® Prime Pro Software ecosystem as applied to AI inference acceleration. Participants progress from FPGA fabric primitives (ALMs, DSP blocks, M20K SRAM, HBM2e) through the Agilex® AI Tensor block architecture, memory subsystem design, AXI4 interfaces, and structured performance benchmarking methodology. The course bridges the conceptual gap between ML model characteristics and FPGA hardware resources, providing the architectural vocabulary and toolchain fluency. Extensive use of Quartus Prime Pro, Platform Designer, Signal Tap, and the Agilex® 5 development kit ensures participants leave with practical device level competency. Course Content: 1. Altera FPGA product portfolio 2. Adaptive Logic Module (ALM) 3. ALM based DSP inference 4. DSP block architecture 5. DSP block chaining 6. M20K embedded SRAM 7. MLAB (MLABCELL) 8. HBM2e architecture 9. Hard IP blocks 10. Clock networks 11. Configuration architecture 12. Power domains 13. DSP with AI Tensor block 14. Supported operating modes 15. Peak throughput calculation 16. AI Tensor block vs. standard DSP mode 17. Systolic array concepts 18. Mapping a GEMM onto AI Tensor blocks 19. Mixed precision inference 20. Energy efficiency benchmarks 21. Accuracy vs. efficiency tradeoffs 22. HBM2e bandwidth requirements for AI Tensor block saturation: weight streaming vs. weight stationary strategies 23. Agilex 9 AI tensor block enhancements and roadmap direction 24. Memory hierarchy for FPGA inference 25. Bandwidth requirements analysis 26. DDR4 and LPDDR4 controller 27. HBM2e controller 28. On-chip buffer strategies 29. Weight tiling and data reuse 30. Activation memory management 31. AXI4 memory mapped protocol 32. AXI4-Stream protocol 33. Avalon-MM and Avalon-ST 34. Platform Designer memory subsystem design 35. Cache coherency models for FPGA HPS systems Prerequisites: - FPGA Authority “ML/AI Essentials for Hardware Engineers” course or equivalent foundational ML knowledge - Basic digital logic: combinational and sequential circuits, state machines - Familiarity with Verilog or SystemVerilog at the RTL concept level - Linux command line proficiency - Basic understanding of computer architecture: memory hierarchy, pipelines, clock domains Tools Required: - Quartus Prime Software Pro Edition - Platform Designer - ModelSim-Altera FPGA Edition / Questa - Signal Tap Logic Analyzer - System Console - Altera VTune Profiler - Python 3.11+ - OpenVINO Toolkit - Agilex 5 FPGA Development Kit Course code: AML-07. FA_AIACC.