Why are there recovery timing violations on the External Memory Interfaces Stratix® 10 FPGA IP for DDR4 reset_sync_pri_sdc_anchor signal? - Why are there recovery timing violations on the External Memory Interfaces Stratix® 10 FPGA IP for DDR4 reset_sync_pri_sdc_anchor signal? Description You might see recovery violations on the reset_sync_pri_sdc_anchor signal due to the automatic global promotion of this reset. Resolution To avoid the violations, apply the following assignment to prevent the signal from being promoted onto a global network: set_instance_assignment -name GLOBAL_SIGNAL OFF -to <hierarchy>|reset_sync_pri_sdc_anchor Custom Fields values: ['novalue'] Troubleshooting 18038644865 False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue No plan to fix ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']