Synthesis Critical Violation: IPC-40026 - System clock frequency mismatch - Synthesis Critical Violation: IPC-40026 - System clock frequency mismatch Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, there will be a critical synthesis violation when using Agilex® 5 GTS SDI II IP with BASE and PHY mode, and set System PLL frequency to a value other than 700MHz. Resolution You can ignore this violation if the System PLL output frequency meets the minimum requirement in Table 25 of the GTS SDI II IP User Guide: SDI Mode Minimum System PLL Output Frequency HD-SDI single rate 150 MHz 3G-SDI single rate 300 MHz Triple rate SDI (up to 3G-SDI) 300 MHz Multi rate SDI (up to 12G-SDI) 600 MHz This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting QS-232914 novalue ['Interfaces Audio/Video SDI II (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']