How is the PLL Fractional Divider value calculated by the Quartus II software when using the Altera PLL megafunction? - How is the PLL Fractional Divider value calculated by the Quartus II software when using the Altera PLL megafunction? Description The attached document describes how the Quartus® II software calculates the PLL Fractional Divison parameter, when using the Altera® PLL megafunction in fractional mode, and how you can enter this value in the Altera PLL megafunction. Related Articles How precise are the output clock frequencies generated by the Altera_PLL megafunction? What is the purpose of the Channel Spacing field, when implementing a fractional PLL in the Altera PLL megafunction? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']