What clock should I use to capture the PIPE interface signals on the test_out bus when using SignalTap II Logic Analyzer? - What clock should I use to capture the PIPE interface signals on the test_out bus when using SignalTap II Logic Analyzer? Description Use pld8gtxclkout to capture the PIPE signals on the test_out interface using the SignalTap ™ II Logic Analyzer. This clock signal is located in the following hierarchy: For Arria ® V device families: * xcvr_native|inst_av_pcs|inst_av_pcs_ch* For Stratix ® V device families: *xcvr_native|inst_sv_pcs|int_sv_pcs_ch* Custom Fields values: ['novalue'] Troubleshooting novalue False ['Basic Functions Clocks (Primary)', 'PCI Express'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']