Can the start_of_burst and end_of_burst signals be asserted at the same time for the Serial Lite III FPGA IP on Arria® 10 and Stratix® 10 devices? - Can the start_of_burst and end_of_burst signals be asserted at the same time for the Serial Lite III FPGA IP on Arria® 10 and Stratix® 10 devices?
Description Yes. The Serial Lite III FPGA IP supports a minimum one cycle burst length for the source data interface. You can assert the start_of_burst and end_of_burst signals on the same clock cycle for one cycle source data. Resolution N/A Additional Information N/A
Custom Fields values:
['novalue']
Troubleshooting
FB: 517278;
False
['Serial Lite III Streaming IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
No plan to fix
19.1
['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2024-10-29
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