Error: Unable to rewrite SYCL IR file - Error: Unable to rewrite SYCL IR file Hi there, I'm building DPC++ for the S10 FPGA and I'm getting the error in the subject. Full command is in the logfile. My supicion is that it is due to the the following clang-offload-bundler -type=ao -targets=host-x86_64-unknown-linux-gnu -input=/home/u177770/gsl/lib/libgsl.a -check-section -base-temp-dir=/home/u177770/tmp/icpx-458e49 clang-offload-bundler -type=o -targets=sycl-spir64-unknown-unknown -input=CMakeFiles/optPricer.profile.dir/fp2bin.cpp.o -check-section -base-temp-dir=/home/u177770/tmp/icpx-458e49 Where the GSL library differs in target to the C++ object files. Any help appreciated! Replies: Re: Error: Unable to rewrite SYCL IR file Hi @aidanom1 , Greetings, as we are receiving a good response from you, hence would assume challenge are overcome. Please login to ‘ https://supporttickets.intel.com’ , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here. Best Wishes BB Replies: Re: Error: Unable to rewrite SYCL IR file Hi @aidanom1 , Greetings, just checking in to see if there is any further doubts in regards to this matter. Hope we have clarify your doubts. Best Wishes BB Replies: Re: Error: Unable to rewrite SYCL IR file Hi @aidanom1 , Thank you for posting in Intel community forum and hope all is well. From the logs that you have shown, it seems that you are trying to compile the design for FPGA hardware, and which it will it would requires hardware of S10 or A10. And from the node that you have accessed, it just a compile node which does not have hardware. Hence would suggest to changed to a node with hardware to try the compilation. Hope that clarify. Best Wishes BB Replies: Re: Error: Unable to rewrite SYCL IR file Hi, I tried building one of the oneAPI samples. Here is my log u177770@login-2:~$ qsub -I -l nodes=1:fpga_compile:ppn=2 -d . qsub: waiting for job 2214690.v-qsvr-1.aidevcloud to start qsub: job 2214690.v-qsvr-1.aidevcloud ready ######################################################################## # Date: Sat 25 Feb 2023 02:34:14 AM PST # Job ID: 2214690.v-qsvr-1.aidevcloud # User: u177770 # Resources: cput=75:00:00,neednodes=1:fpga_compile:ppn=2,nodes=1:fpga_compile:ppn=2,walltime=06:00:00 ######################################################################## u177770@s001-n059:~$ git clone -b 2023.0.0 https://github.com/oneapi-src/oneAPI-samples.git Cloning into 'oneAPI-samples'... remote: Enumerating objects: 24137, done. remote: Counting objects: 100% (585/585), done. remote: Compressing objects: 100% (352/352), done. remote: Total 24137 (delta 245), reused 521 (delta 223), pack-reused 23552 Receiving objects: 100% (24137/24137), 256.24 MiB | 3.35 MiB/s, done. Resolving deltas: 100% (15683/15683), done. Note: switching to 'cb1440584bb64554d573bf7b03225926c2da3651'. You are in 'detached HEAD' state. You can look around, make experimental changes and commit them, and you can discard any commits you make in this state without impacting any branches by switching back to a branch. If you want to create a new branch to retain commits you create, you may do so (now or later) by using -c with the switch command. Example: git switch -c <new-branch-name> Or undo this operation with: git switch - Turn off this advice by setting config variable advice.detachedHead to false Updating files: 100% (3353/3353), done. u177770@s001-n059:~$ cd oneAPI-samples/ AI-and-Analytics/ common/ DirectProgramming/ .git/ .github/ Libraries/ Publications/ RenderingToolkit/ Tools/ u177770@s001-n059:~$ cd oneAPI-samples/DirectProgramming/ C++/ DPC++/ DPC++FPGA/ Fortran/ u177770@s001-n059:~$ cd oneAPI-samples/DirectProgramming/DPC++FPGA/ include/ ReferenceDesigns/ Tutorials/ u177770@s001-n059:~$ cd oneAPI-samples/DirectProgramming/DPC++FPGA/ReferenceDesigns/ anr/ cholesky/ crr/ decompress/ merge_sort/ qrd/ board_test/ cholesky_inversion/ db/ gzip/ mvdr_beamforming/ qri/ u177770@s001-n059:~$ cd oneAPI-samples/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/ u177770@s001-n059:~/oneAPI-samples/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test$ mkdir build u177770@s001-n059:~/oneAPI-samples/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test$ cd build u177770@s001-n059:~/oneAPI-samples/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/build$ cmake .. -DFPGA_DEVICE=/opt/intel/oneapi/intel_s10sx_pac:pac_s10 -- The CXX compiler identification is Clang 16.0.0 -- Check for working CXX compiler: /glob/development-tools/versions/oneapi/2023.0.1/oneapi/compiler/2023.0.0/linux/bin/icpx -- Check for working CXX compiler: /glob/development-tools/versions/oneapi/2023.0.1/oneapi/compiler/2023.0.0/linux/bin/icpx -- works -- Detecting CXX compiler ABI info -- Detecting CXX compiler ABI info - done -- Detecting CXX compile features -- Detecting CXX compile features - done -- Configuring the design to run on FPGA board /opt/intel/oneapi/intel_s10sx_pac:pac_s10 -- Configuring done -- Generating done -- Build files have been written to: /home/u177770/oneAPI-samples/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/build u177770@s001-n059:~/oneAPI-samples/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/build$ make fpga Scanning dependencies of target board_test.fpga [ 50%] Building CXX object src/CMakeFiles/board_test.fpga.dir/board_test.cpp.o [100%] Linking CXX executable ../board_test.fpga warning: -reuse-exe file '/home/u177770/oneAPI-samples/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/build/board_test.fpga' not found; ignored aoc: Compiling for FPGA. This process may take several hours to complete. Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets. If the reports indicate performance targets are not being met, code edits may be required. Please refer to the oneAPI FPGA Optimization Guide for information on performance tuning applications for FPGAs. Error (23035): Tcl error: Error (23031): Evaluation of Tcl script build/entry.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings For more details, full Quartus compile output can be found in files quartuserr.tmp and quartus_sh_compile.log. Error: Compiler Error, not able to generate hardware llvm-foreach: icpx: error: fpga compiler command failed with exit code 1 (use -v to see invocation) make[3]: *** [src/CMakeFiles/board_test.fpga.dir/build.make:84: board_test.fpga] Error 1 make[2]: *** [CMakeFiles/Makefile2:127: src/CMakeFiles/board_test.fpga.dir/all] Error 2 make[1]: *** [CMakeFiles/Makefile2:215: src/CMakeFiles/fpga.dir/rule] Error 2 make: *** [Makefile:170: fpga] Error 2 u177770@s001-n059:~/oneAPI-samples/DirectProgramming/DPC++FPGA/ReferenceDesigns/board_test/build$ Replies: Re: Error: Unable to rewrite SYCL IR file Hi, Thanks for posting in Intel communities. Could you please provide us with a sample reproducer code & complete steps to reproduce your issue from our end? Thanks & Regards, Santosh