Why does the Intel Agilex® 7 F-Tile PMA/FEC Direct PHY Intel® FPGA IP Design Example fail to simulate when using Intel® Quartus® Prime Pro Edition Software version 23.1? - Why does the Intel Agilex® 7 F-Tile PMA/FEC Direct PHY Intel® FPGA IP Design Example fail to simulate when using Intel® Quartus® Prime Pro Edition Software version 23.1? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, the Intel Agilex® 7 F-Tile PMA/FEC Direct PHY Intel® FPGA IP configured to generate an FHT PAM4 4 400G 4 PMA Lanes RSFEC 544/514 design example will fail to simulate. Resolution To workaround this problem in the Intel® Quartus® Prime Pro Edition Edition Software version 23.1, change the select FHT loopback mode attribute from DISABLED to SERIAL_EXT_LOOPBACK mode and re-generate the IP. This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 23.2. Custom Fields values: ['novalue'] Troubleshooting 16020640788 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 23.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']