DSP Builder Advanced Blockset: Interfaces and IP Libraries - 25 Minutes The DSP Builder for Altera® FPGAs is a collection of library blocks for the Mathworks* Matlab* Simulink* environment that allows you to generate device-optimized high-performance DSP systems for Altera® FPGAs. In this training we will discuss how to use the blocks in the Interfaces and IP libraries within the DSP Builder Advanced Blockset. We will discuss the default interfaces of the DSP Builder and how to create custom streaming and memory-mapped interfaces to interact with external components. We will also cover the functionality provided by IP blocks which makes it easy to implement FFTs, channel filters, and waveform synthesis blocks. *Other names and brands may be claimed as the property of others Course Objectives At course completion, you will be able to: use streaming library blocks to Create Avalon streaming inputs and outputs use memory mapped library blocks to Create Custom registers and memories accessible from the host processor interface use IP blocks to Implement FFTs, Filters, and Waveform Synthesis functions Constrain latency of IP blocks Skills Required Basic knowledge of MATLAB, Simulink and the Altera® Quartus® Prime software Basic understanding of the DSP Builder for Altera® FPGAs If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODSPINTIP. FPGA_ODSPINTIP. <p>DSP Builder Advanced Blockset: Interfaces and IP Libraries</p>