Why does the VHDL wrapper file generated for DDR3 SDRAM Controller with UniPHY fail to compile in Quartus II software version 11.0? - Why does the VHDL wrapper file generated for DDR3 SDRAM Controller with UniPHY fail to compile in Quartus II software version 11.0? Description Compiling a VHDL version of a DDR3 with UniPHY core in the Quartus ® II software version 11.0 results in the following error during synthesis: Error: Illegal connection found on I/O input buffer primitive heirarchy |altdq_dqs2_ddio_3reg_stratixiii:altdq_dqs2_inst|obuf_os_0 also drives out to other destination than the buffer. The top-level wrapper file is a VHDL file that instantiates a Verilog version of the core. All single bit signals (mem_cas_n, mem_we_n, mem_ck, mem_odt, mem_cs_n, mem_cke, mem_ras_n, and mem_ck_n) are defined as std_logic_vector(0 downto 0) in the top-level and are defined as signle bit wires in the instantiated core. The Quartus II software currently cannot resolve this connection between single bit VHDL std_logic_vector definitions and single bit Verilog wires, which results in the above error. The workaround is to change the single bit signals in the top-level VHDL wrapper from std_logic_vector(0 downto 0) to std_logic. This issue is scheduled to be fixed in a future release of the Quartus II software. Related Articles Error (332000): ERROR: Argument node_object is an object filter that matches no objects. Specify one matches only one object Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® III FPGAs'] ['novalue'] ['novalue'] ['novalue']