Introduction to the Low Latency 10Gb Ethernet MAC Altera® FPGA IP Core - 38 Minutes This online course will instruct you in how to use Altera® IP solutions to build a 10Gb Ethernet design targeting Altera® transceiver devices, using the Quartus® Prime Pro software. In this course, you will learn how the Low Latency 10Gb Ethernet MAC IP is a flexible solution, providing many ways to customize and control its behavior for your application. You will learn how to configure the IP and how to incorporate it into your design. Course Objectives At course completion, you will be able to: Describe the features and functionality of the Low Latency 10Gb Ethernet MAC IP core Configure an IP instance using the Low Latency 10Gb Ethernet MAC IP parameter editor Skills Required Familiarity with common high-speed transceiver architecture OR viewing the appropriate "Transceiver Basics" training for your targeted device Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus Prime Pro design software Some familiarity with Platform Designer system building tool If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_O10GMAC. FPGA_O10GMAC. <p>Introduction to the Low Latency 10Gb Ethernet MAC Altera FPGA IP Core</p>