Why does the outclk of the ALTCLKCTRL IP remain enabled when using the ENA input in External Path mode? - Why does the outclk of the ALTCLKCTRL IP remain enabled when using the ENA input in External Path mode? Description Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 or earlier, you might see that the output clock of the ALTCLKCTRL IP remains enabled regardless of whether the ENA input is asserted or de‑asserted when using the “External path” mode. This problem occurs because the ENA input port is not used in “External path” mode even if the “Create ‘ena’ port to enable or disable the clock network driven by this buffer” option is selected. Beginning with the Quartus® Prime Standard Edition Software version 23.1, the software will generate an error message indicating that the “Create ‘ena’ port” option is unavailable when the “External path” type is selected. Resolution To work around this problem using the ALTCLKCTRL IP with the “External path” mode: Disable the “Create ‘ena’ port to enable or disable the clock network driven by this buffer” option in the Parameter Editor. If you require clock gating, implement the gating logic external to ALTCLKCTRL (for example, gate the source clock or use an alternate supported clock‑control scheme) rather than relying on the ALTCLKCTRL ENA port in “External path” mode. Custom Fields values: ['novalue'] Troubleshooting 1507287234 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 25.1 23.1 ['Arria® 10 FPGAs and SoCs', 'Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® 10 LP FPGA', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'MAX® 10 FPGAs', 'MAX® II CPLDs', 'MAX® V CPLDs'] ['novalue'] ['novalue'] ['novalue']