Why do I see minimum pulse width violations when using the Enable refclock to core feature in the GTS PMA/FEC Direct PHY FPGA IP on Agilex™ 5 devices when using the Quartus Prime Pro Edition Software version 24.1? - Why do I see minimum pulse width violations when using the Enable refclock to core feature in the GTS PMA/FEC Direct PHY FPGA IP on Agilex™ 5 devices when using the Quartus Prime Pro Edition Software version 24.1? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, using the Enable refclock to core feature in the GTS PMA/FEC Direct PHY FPGA IP for Agilex™ 5 devices may result in a minimum pulse width violation. Resolution The timing of the Enable refclock to core feature on Agilex™ 5 devices is preliminary in Quartus® Prime Pro Edition Software version 24.1. It is safe to ignore this violation. This problem will be fixed in a future version of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16023591351 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']