Why can't QSPI flash be accessed using the Mailbox Client Intel® FPGA IP in designs that include HPS? - Why can't QSPI flash be accessed using the Mailbox Client Intel® FPGA IP in designs that include HPS? Description In Intel® Stratix® 10 and Intel Agilex® 7 devices with HPS, due to the implementation of HPS software, once the HPS is released from reset, you cannot access QSPI flash using the Mailbox Client Intel® FPGA IP. You will see error code 0x81 (QSPI_ALREADY_OPEN) for QSPI_OPEN operation (Please refer to Mailbox Client Intel® FPGA IP User Guide for the details of the operation command and error codes). Resolution This is expected behavior. In designs which include HPS, both SDM and HPS cannot access the shared QSPI flash simultaneously. Custom Fields values: ['novalue'] Troubleshooting 1509114777 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 21.1 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']