How do I decide when to compensate for the package delay mismatch (Package Deskew) when routing the board traces for my memory interface? - How do I decide when to compensate for the package delay mismatch (Package Deskew) when routing the board traces for my memory interface? Description Package deskew is not required for any memory protocol operating at 800 MHz or below. Resolution For DDR3 and RLDRAM3 design operating above 800 MHz, Intel recommends that you run the timing analysis with accurately entered board skew parameters in the intellectual property (IP) parameter editor. Only if you are getting non-core timing violations in the 'Report DDR' Timing report then you should apply the steps mentioned in the ‘Package Deskew’ section of the Volume 2 Chapter 4 of the EMIF Handbook. The recommendation may be different from the solution shown in the External Memory Interface Handbook. Intel is in the process of updating the handbook. Custom Fields values: ['novalue'] Troubleshooting 2205725613 False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']