Why does the Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP fail at “Fitter” when implementing multiple instances? - Why does the Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP fail at “Fitter” when implementing multiple instances? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.1 and earlier, you might observe a fitter error when two Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IPs are instantiated in one project. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.2. Custom Fields values: ['novalue'] Troubleshooting 18027959000 False ['R-Tile for Compute Express Link Solution'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 22.4 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']