Why does my Altera Hard IP for PCI Express not enter compliance loopback in Gen 3 mode? - Why does my Altera Hard IP for PCI Express not enter compliance loopback in Gen 3 mode? Description The Altera® Hard IP core for PCI® Express will not enter compliance loopback mode at Gen3 rates if the compliance receive bit in the configuration register space, has not been set by the loopback master. Resolution To comply with the PCI Express Specification, ensure your loopback master sets the compliance receive bit correctly. Related Articles Does IP Compiler for PCIe support automatic Compliance mode detection during Compliance Base Board (CBB) testing? Custom Fields values: ['novalue'] Troubleshooting novalue False ['PCI Express'] ['novalue'] novalue novalue ['Arria® V GZ FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']