Why is my DDR2 UniPHY controller interface only 50% efficient for back-to-back read or write commands? - Why is my DDR2 UniPHY controller interface only 50% efficient for back-to-back read or write commands? Description The High Performance Controller II (HPCII) used by the DDR2 UniPHY and ALTMEMPHY cores issues back to back read/write commands on every other controller clock cycle ( afi_clk ). If you have the burst length set to 4 for a half rate controller, then the controller will only use 50% of the maximum efficiency on the bus. This is an expected behavior of the half rate controller for burst length of 4 implementation. Resolution There are two workarounds: Use a full-rate HPCII controller when you set the burst length to 4. Use a half-rate HPCII controller when you set the burst length to 8. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']