Does the Advanced clock phase control adjustment in the HPS DDR3 work? - Does the Advanced clock phase control adjustment in the HPS DDR3 work? Description You may notice the Advanced clock phase control setting in the HPS GUI PHY Settings tab. Changing the phase value has no effect on the phase of the PLL output clocks. Resolution The Advanced clock phase control adjustment will be removed in a future version of the Quartus® II software. This problem was fixed in Quartus® II software version 13.1 Custom Fields values: ['novalue'] Troubleshooting 1408035040 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 13.0 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']