VCS generates this warning when doing a functional simulation of the DDR, DDR2 and DDR3 SDRAM High Performance Controller II IP. This warning appears because the code is connecting a 1-bit LSB of a 4 bit bus to a 2-bit input - VCS generates this warning when doing a functional simulation of the DDR, DDR2 and DDR3 SDRAM High Performance Controller II IP. This warning appears because the code is connecting a 1-bit LSB of a 4 bit bus to a 2-bit input Description VCS generates this warning when doing a functional simulation of the DDR, DDR2 and DDR3 SDRAM High Performance Controller II IP. This warning appears because the code is connecting a 1 -bit LSB of a 4 bit bus to a 2 -bit input, so bit 2 of the clk_reset scan_din input is undriven. The leveled sequencer does not use scan chains on mem_clks and this doesn't matter for a non-levelled design (i.e, DDR2) since it doesn't use the scan chains either. Hence this message can be safely ignored. Warning-[PCWM-W] Port connection width mismatch &ltpath_name>/SdramController_PLL_Master_phy_alt_mem_phy.v, 1395"clk". The following 1-bit expression is connected to 2-bit port "scan_din" of module "SdramController_PLL_Master_phy_alt_mem_phy_clk_reset", instance "clk" Expression: scan_din[0] use lint=PCWM for more details Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']