Timing Violation for Clocked Video Output in HDMI Arria V Design Example - Timing Violation for Clocked Video Output in HDMI Arria V Design Example Description When you run the HDMI Arria V design example ( av_sk ) , you may encounter timing violation on the clocked video output path. Resolution There is no workaround for this issue. This issue will be fixed in a future version of the HDMI IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']