Can I connect a single dedicated reference clock pin to 2 separate IOPLLs using the dedicated IOPLL clock path in an Intel Agilex® 7 FPGA or Intel® Stratix® 10 device? - Can I connect a single dedicated reference clock pin to 2 separate IOPLLs using the dedicated IOPLL clock path in an Intel Agilex® 7 FPGA or Intel® Stratix® 10 device? Description No, a single dedicated reference clock pin cannot connect to 2 separate IOPLLs using the dedicated IOPLL clock path in an Intel Agilex® 7 FPGA or Intel® Stratix® 10 device. Resolution To connect a single dedicated reference clock pin to 2 separate IOPLLs then you must either: A) Use a global clock network for the 2nd IOPLL. or B) Cascade the 2 IOPLLs. Custom Fields values: ['novalue'] Troubleshooting 18016501428 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.1 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® FPGAs'] ['novalue'] ['novalue'] ['novalue']