Possible Enumeration Failure for Stratix V Hard IP for PCI Express Gen3 x8 - Possible Enumeration Failure for Stratix V Hard IP for PCI Express Gen3 x8 Description Gen 3 x8 variants of the Stratix V GX Hard IP for PCI Express IP Core may fail during enumeration when the adaptive equalization (AEQ) is active during the LTSSM speed change state. Resolution This issue is fixed in version 12.1 SP1 of the Hard IP for PCI Express IP Core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.1.1 12.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']