Why can’t I achieve the specified timestamp accuracy results with the multi-lane F-Tile Ethernet FPGA Hard IP variant with the “Enable IEEE 1588 PTP” parameter enabled and the “FEC Mode” parameter set to “None”? - Why can’t I achieve the specified timestamp accuracy results with the multi-lane F-Tile Ethernet FPGA Hard IP variant with the “Enable IEEE 1588 PTP” parameter enabled and the “FEC Mode” parameter set to “None”? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, the multilane (i.e. 40GE-4, 50GE-2 and 100GE-4) F-Tile Ethernet FPGA Hard IP variants with the “Enable IEEE 1588 PTP” parameter enabled and the “FEC Mode” parameter set to “None” will fail to achieve the specified timestamp accuracy results. This problem does not affect single-lane PTP variants (i.e., 10GE-1 and 25GE-1) with the “FEC Mode” parameter set to “None”. Resolution There is no workaround for this problem. Multilane F-Tile Ethernet FPGA Hard IP variants with the “FEC Mode” parameter set to “None” should not be used for IEEE 1588 PTP applications. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Errata 14023325536 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']