Why do I see IO failures in my Hard Processor System Design? - Why do I see IO failures in my Hard Processor System Design? Description Due to a problem in the Altera Embedded Design Suite (EDS) version 13.0, HPS IO pins that are not used by the peripherals you have selected, may be set to the wrong IO state by the prelaoder causing functional failures. Resolution To workaround this issue in the Altera Embedded Command Shell version 13.0, all IO pins not in use by Peripherals MUST be set to GPIO. Pins can be set to GPIO by selecting YES in the GPIO Enabled column of the Conflicts window on the Peripheral Pin Multiplexing tab of the Hard Processor System MegaCore MegaWizzard. This problem is scheduled to be fixed in the next release of the Altera Embedded Design Suite (EDS). Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']