IP SDC: Could not find active CLKOUT ports for user facing clocks can't read "top_fab_inst_name": no such variable while executing "get_registers -nowarn ${top_fab_inst_name}hdpldadapt_tx_chnl_*~aib_fabric_pma_aib_tx_clk.reg" - IP SDC: Could not find active CLKOUT ports for user facing clocks can't read "top_fab_inst_name": no such variable while executing "get_registers -nowarn ${top_fab_inst_name}hdpldadapt_tx_chnl_*~aib_fabric_pma_aib_tx_clk.reg" Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, you may see this error during compilation of the implementation revision, when partial reconfiguration is enabled and the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* is being used: IP SDC: Could not find active CLKOUT ports for user facing clocks can't read "top_fab_inst_name": no such variable while executing "get_registers -nowarn ${top_fab_inst_name}hdpldadapt_tx_chnl_*~aib_fabric_pma_aib_tx_clk.reg" invoked from within "set hdpldadapt_tx_pld_rst_n [get_registers -nowarn ${top_fab_inst_name}hdpldadapt_tx_chnl_*~aib_fabric_pma_aib_tx_clk.reg]" (file "../../../../modules/c7_chip/main/src/tech/agilexf/map800_2vr0/ip_pcie_st_gen3x4/pcie_avst_f_600/synth/pcie_f_ip.sdc" line 440) ERROR: An error occurred during automatic periphery placement Resolution To work around this problem, remove the FAST_PRESERVE assignment, as F-Tile cannot be used with fast preservation. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15012220478 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']