In DDR2 and DDR3 SDRAM Controller with UniPHY, Example Designs Without DM Pins Enabled Will Fail - In DDR2 and DDR3 SDRAM Controller with UniPHY, Example Designs Without DM Pins Enabled Will Fail Description Any generated example design that does not have DM pins enabled will fail in simulation and in hardware. Resolution There is no workaround for this issue. Custom Fields values: ['novalue'] Troubleshooting novalue True ['Simulation'] ['FPGA Dev Tools Quartus II Software'] 11.1 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']