Access for Stratix 10 node - Access for Stratix 10 node Currently I have an account to DevCloud, and I used oneAPI to implement my work with Stratix 10 board chosen. However, it seems like I have to access Stratix 10 PAC node to run my work (instead of Stratix 10 oneAPI node), which I don't have access. I tried to sign up for the c009-fpga group following the last section of this post I kept running into the same error message telling me there can't be any special character in the input box, I have checked/retype many times and I can't tell if there was ANY special character. Would someone please just add me to the c009-fpga group? My account number is u47712. Replies: Re: Access for Stratix 10 node Hi, Glad to hear that the issue is resolved. Yes, I think the segmentation fault might be related to the kernel or your host code to kernel interface. Replies: Re: Access for Stratix 10 node Thanks, I did not do initialize The FPGA before. Now it does not show (CL_INVALID_BINARY) anymore. It runs into segmentation fault though, I guess there are some issues in the kernel code? If so, I think I am good with this S10 board problem and should focus on debugging the kernel from now. Thank you. Replies: Re: Access for Stratix 10 node Hi, Have you try initialize the board? You may refer to https://software.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/programming-interface/fpga-flow/fpga-bsps-and-boards/fpga-board-initialization.html for more information. Replies: Re: Access for Stratix 10 node Hi, I run " aocl diagnose" and it passed, seems like there's no problem with The FPGA card. May I ask what you mean by "program the FPGA" ? I ran the following commands, not sure if this is what you meant: $ dpcpp -fintelfpga ../src/fuse.cpp -c -o dev.o $ dpcpp -fintelfpga -fsycl-link=image dev.o -o device_image.a -Xshardware -Xsboard=intel_s10sx_pac:pac_s10 $ dpcpp -fintelfpga ../src/host.cpp -c -o host.o $ dpcpp -fintelfpga host.o device_image.a -o FUSE.fpga ------------------------------------------------------------- I run the xxx.FPGA again, this time I got segmentation fault instead of (CL_INVALID_BINARY) Replies: Re: Access for Stratix 10 node Hi, The API node that you connected should have the Stratix 10 PAC card connected. You should be able to performed "aocl diagnose". May I know if you program the FPGA before you proceed with the host code? Replies: Re: Access for Stratix 10 node Hi, I am able to access the S10 oneAPI node and compile my work or run emulation, but I cannot run my program ( xxx.FPGA) on the node. When my host code calls the kernel function, it shows: " terminate called after throwing an instance of 'cl::sycl::runtime_error' what(): Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY). Aborted" I think maybe I need to connect to the S10 PAC node instead to run the xxx.FPGA file? Thanks. Replies: Re: Access for Stratix 10 node Hi, May I know what is the selection that you are able to select when you input "devcloud_login"? Are you able to access the Stratix 10 OneAPI node? If no, what is the error observed? Thanks. John Tio