Why is an error message shown when generating the F-Tile Ethernet Intel® FPGA Hard IP Multi-instance IP core example design enabled with the SyncE feature? - Why is an error message shown when generating the F-Tile Ethernet Intel® FPGA Hard IP Multi-instance IP core example design enabled with the SyncE feature? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, you might see an error message in the System Messages tab of the IP Catalog when both the following conditions are met: Enable dedicated CDR clock output option in the IP tab is checked to enable SyncE feature. Multi instance of IP core menu is selected in the Example Design tab Resolution To work around this problem, you can generate a separate "Single Instances of IP core" enabled with SyncE feature and stitch them together for multi instances manually. For example, you can refer to the diagram "Clock Connection of Sync-E clock through CDR clock out pin" described in the F-Tile Ethernet Intel® FPGA Hard IP User Guide. This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.4. Custom Fields values: ['novalue'] Troubleshooting 16017989562 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 22.3 ['Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['novalue']