Why does the reset_status signal toggles after pin_perst signal is released in the Stratix® V Avalon® ST Interface for PCIe* IP? - Why does the reset_status signal toggles after pin_perst signal is released in the Stratix® V Avalon® ST Interface for PCIe* IP? Description When using the Stratix® V Avalon®-ST Interface for PCIe* IP, you may observe the reset_status signal toggling after pin_perst is released and before ltssmstate signal reaches Polling.Active (0x2). You can safely ignore this behavior and sample reset_status signal until the ltssmstate signal is greater than Polling.Active (0x2). Resolution This information is scheduled to be added in a future release of the Stratix® V Avalon® ST Interface for PCIe* Solution User Guide. Custom Fields values: ['novalue'] Troubleshooting 2007806331 True ['Stratix® V Hard IP for PCI Express IP'] ['FPGA Dev Tools Quartus® Prime Software Standard', 'FPGA Dev Tools Quartus II Software'] novalue 15.1.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25