Why does the Intel® Arria® 10 DisplayPort IP with Bitec* daughter card have no video output for both 1-lane or 2 lanes configurations? - Why does the Intel® Arria® 10 DisplayPort IP with Bitec* daughter card have no video output for both 1-lane or 2 lanes configurations? Description Due to a problem with the Intel® Arria® 10 DisplayPort IP in the Intel® Quartus® Prime Pro Edition Software version 17.1, DisplayPort IP configured for 1 lane or 2 lanes will not have a video output when paired with Bitec* daughter card rev8 and below. This is due to the DisplayPort IP core transmitting the video through lanes fmca_dp_c2m_n[0] & fmca_dp_c2m_n[1] when it is set to 2 lanes. The signals are mapped to lanes 2 & 3 of the Bitec daughter card's DisplayPort Transmitter connector for lane reversal and polarity inversion support. The DisplayPort sink (monitor) expects display port training patterns at lanes 0 and 1 of the DisplayPort connector. Hence, this results in the link training between the DisplayPort source-sink will fail and ending up with no video output failure. Resolution To work around this problem, manually remap DisplayPort IP lane[0] and lane[1] pin location assignment with reference to the table guideline. Step 1: Disable all of the XCVR_RECONFIG_GROUP on channels 0 to 3 in the QSF . For instance : set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to fmca_dp_c2m_p[0] -entity a10_dp_demo set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to fmca_dp_m2c_p[0] -entity a10_dp_demo Step 2: Modify DisplayPort IP lane pin assignment in the QSF as per the table guideline Custom Fields values: ['novalue'] Troubleshooting 2205894323 False ['DisplayPort'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']