VIP 2D FIR Filter and Color Space Converter Blocks Produce Incorrect Outputs in Hardware - VIP 2D FIR Filter and Color Space Converter Blocks Produce Incorrect Outputs in Hardware Description Signed multipliers are interpreted as unsigned multipliers, resulting in unexpected output data from the following cores: 2D finite impulse response (FIR) filter Color space converter (CSC) This issue is not observable in simulation, but is visible at the hardware or gate-level simulations in version 12.0 release for the Stratix V, Arria V, and Cylone V devices. Resolution None. This issue is fixed in 12.0sp1. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']