Why do I see Timing violations in the Intel® Stratix® V and Arria® V GZ devices when using the Intel® 50G and 100G Interlaken MegaCore® Function IP. - Why do I see Timing violations in the Intel® Stratix® V and Arria® V GZ devices when using the Intel® 50G and 100G Interlaken MegaCore® Function IP. Description Due to a problem with the Intel® 50G and 100G Interlaken MegaCore® Function IP auto-generated sdc file, setup and recovery timing closure violations my be seen in 24 lane configurations with data rate 6.25G in the Intel® Quartus® Prime Standard versions 18.1.1 and earlier. Resolution To work around this problem, when using the Intel® Quartus® Prime Standard versions 18.1.1 and earlier, replace the auto-generated ilk_core.sdc file with the version attached below. ilk_core.sdc This problem has been fixed starting with the Intel® Quartus® Prime Standard version 19.1 Custom Fields values: ['novalue'] Troubleshooting 1507266844 True ['Interlaken - 100G for 28nm and 20nm devices (PRIMARY) IP-ILKN/100G', 'Interlaken - 50G for 28nm and 20nm devices (PRIMARY) IP-ILKN/50G'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 19.1 18.1.1 ['Arria® V GZ FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-10