Error (169058): I/O standard SSTL-135 on output I/O pin cannot have Termination logic option setting Off - Error (169058): I/O standard SSTL-135 on output I/O pin cannot have Termination logic option setting Off Description You might receive the error above when using general purpose I/O pins and dual-purpose pins (such as INIT_DONE and CRC_ERROR ) in a bank where VCCIO is set to 1.35 V, which is the voltage for the SSTL-135 standard used with DDR3L DRAM devices. This error is because the SSTL-135 I/O standard only supports 34. / 40. termination for outputs. Resolution To work around the problem, add the following assignments to each general-purpose pin: set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to <pin name> set_instance_assignment -name IO_STANDARD "SSTL-135" -to <pin_name> For INIT_DONE , <pin_name> should be set to ~ALTERA_INIT_DONE~ . For CRC_ERROR , the <pin_name> should be set to ~ALTERA_CRC_ERROR~ . Related Articles When using UniPHY IP in Stratix ® V devices, what are the options for changing the calibrated OCT termination values from the default values ? Custom Fields values: ['novalue'] Troubleshooting 2205722749 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix No plan to fix ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']