Why might I see incorrect clock frequency in the khz_rx (0x341) and khz_tx (0x342) registers of E-Tile Hard IP for Ethernet Intel® FPGA IP ? - Why might I see incorrect clock frequency in the khz_rx (0x341) and khz_tx (0x342) registers of E-Tile Hard IP for Ethernet Intel® FPGA IP ? Description You might see incorrect frequency in the khz_rx (0x341) and khz_tx (0x342) registers of E-Tile Hard IP for Ethernet Intel® FPGA IP if the i_reconfig_clk frequency is not 100 MHz. Because the frequency value is measured on the assumption that the i_reconfig_clk frequency is 100 MHz. Resolution If the i_reconfig_clk frequency is not 100 MHz, the khz_rx (0x341) and khz_tx (0x342) register values are calculated with the equation below, respectively. khz_rx (0x341) : Recovered clock frequency /10* [100 MHz / i_reconfig_clk (MHz) ], in KHz khz_tx (0x342) : TX clock frequency /10* [100 MHz / i_reconfig_clk (MHz) ], in KHz The description problem is scheduled to be fixed in a future release of the UG-20160. Custom Fields values: ['novalue'] Troubleshooting 14013808158 True ['E-tile Hard IP for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 19.4 ['Agilex™ 7 FPGA I-Series', 'Stratix® 10 DX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']