Why do I see cache coherency problems between the HPS and FPGA on Intel Agilex® 7 FPGA SoC designs in Intel® Quartus® Prime Pro Edition Software version 20.4 and earlier? - Why do I see cache coherency problems between the HPS and FPGA on Intel Agilex® 7 FPGA SoC designs in Intel® Quartus® Prime Pro Edition Software version 20.4 and earlier? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.4 and earlier, cache coherency errors may be seen on Intel Agilex® 7 FPGA SoC designs for transactions via the FPGA to SOC bridge. Resolution A patch to work around this problem has been released for u-boot-socfpga and is available on https://github.com/altera-opensource/u-boot-socfpga starting with the following branches https://github.com/altera-opensource/u-boot-socfpga V2020.10 HSD #14012926793: cache: ncore: Disable snoop filter Commit date: March 31, 2021 commit ID c79c23c6201819ca32b6739eff2e2b25e19f6624 This patch is included in later branches. Custom Fields values: ['novalue'] Troubleshooting 14012926793 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 20.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']