Why are there bit errors when I perform an RTL simulation of an external serial loopback on Stratix V and Arria V transceiver devices? - Why are there bit errors when I perform an RTL simulation of an external serial loopback on Stratix V and Arria V transceiver devices? Description You may see bit errors when performing an RTL simulation of an external serial loopback of Stratix® V and Arria® V transceiver devices due to a Mentor Graphics Modelsim® resolution and rounding issue. Resolution To work around this issue, you should set the precision of the simulation to fs. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']