What is the difference between these two clear signals? - What is the difference between these two clear signals? Hi, I’m currently investigating an issue. I’m using an FPGA SCFIFO to replace a 72V251 FIFO, with rclk = wclk. I found that if I keep rebooting the device, my industrial camera occasionally shows image tearing. However, this does not happen every time, and my pixel clock is only 36 MHz, so I would not consider it a very high frequency. Could I ask what the difference is between these two FIFO reset options? Asynchronous clear Synchronous clear (flush the FIFO) Replies: Re: What is the difference between these two clear signals? Hi MartinMaa , I'm glad that your issue is resolved. I will proceed with closing this case. We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, ZiYingE_Altera Replies: Re: What is the difference between these two clear signals? Hi, ZiYingE These issues have now been resolved. Thank you. Replies: Re: What is the difference between these two clear signals? Thanks, sstrell , for sharing the documentation link. Hi MartinMaa , Regarding the image tearing issue, I noticed that you had previously filed a support ticket for a similar problem. May I check is issue has been resolved? For the differences between synchronous clear and asynchronous clear, you may refer to the documentation link shared by sstrell , at Section 1.7 FIFO Synchronous Clear and Asynchronous Clear Effect. Regards, ZiYingE_Altera Replies: Re: What is the difference between these two clear signals? All documented: https://docs.altera.com/r/docs/683522/25.1.1/fifo-ip-user-guide/fifo-synchronous-clear-and-asynchronous-clear-effect