Schematic Symbol Parameter in Hex - Schematic Symbol Parameter in Hex Hello, how can I input a hexadecimal value in the parameter table of a block diagram/schematic file (.bdf)? behind the block is the following VHDL code: entity reg is generic ( constant REG_BASE_ADDR : natural := 16#4010#; ); port ( ... ); end; every variant I could imagine results in an error like: Parameter | Value | Type REG_BASE_ADDR | x"4010" | Auto Error (10515): VHDL type mismatch error at reg.vhd(17): natural type does not match string literal Replies: Re: Schematic Symbol Parameter in Hex Not exactly the same, but it will do, thanks. Replies: Re: Schematic Symbol Parameter in Hex Hi, Done testing. Use the following for example: addr : std_logic_vector(15 downto 0) := x"FFFF" Then change line 16 from: signal reg : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(addr, 16)); to: signal reg : std_logic_vector(15 downto 0) := addr; You'll be able to use Hexadecimal type for example value AAAA Thanks, Best Regards, Sheng Replies: Re: Schematic Symbol Parameter in Hex The one you get by clickling File -> Create/Update -> Create Symbole Files from Current File in the*.vhd file. the upper block with with Verilog works, VHDL does not. Replies: Re: Schematic Symbol Parameter in Hex Hi, May I know which block you're using in .bdf? Thanks, Regards, Sheng Replies: Re: Schematic Symbol Parameter in Hex This does not work. here is some test code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test2 is generic ( addr : natural := 16#4000# ); port ( i_clk : in std_logic; o : out std_logic_vector(15 downto 0) ); end; architecture arch of test2 is signal reg : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(addr, 16)); begin o <= reg; end; generating a symbol from this code results in the following table: Parameter | Value | Type addr | 16384 | Signed Integer and synthesizes correctly to using Parameter | Value | Type addr | 4000 | Hexadecimal results in an error: Error (10515): VHDL type mismatch error at /asd.vhd(8): natural type does not match string literal using Parameter | Value | Type addr | 4000 | Auto synthesizes incorrectly to: Replies: Re: Schematic Symbol Parameter in Hex Hi, To input a hexadecimal value in the parameter table of a block diagram/schematic file (.bdf), set the (Type) to either Auto or Hexadecimal then under (Value) straight away give a value for example like: a, not need the symbol x"" Thanks, Regards, Sheng Replies: Re: Schematic Symbol Parameter in Hex I'm using Quartus Prime Lite 22.1.2 and 23.1 With verilog it works for me like so: Parameter | Value | Type REG_BASE_ADDR | 4002 | Hexadecimal But something like X"4000" or 16#4000# is not a VHDL-2008 thing, or is it? Replies: Re: Schematic Symbol Parameter in Hex Hi, the problem doesn't seem related to VHDL support in my view. You can neither send a hexadecimal literal to a numerical Verilog module parameter. Only decimal numbers seem to be accepted as block parameters for numerical values. Replies: Re: Schematic Symbol Parameter in Hex Assuming you are using Standard or Lite, you may be running into the limited VHDL 2008 support there: https://community.intel.com/t5/Programmable-Devices/Does-Quartus-20-1-std-support-VHDL-2008-vector-aggregation/m-p/1468730#M90058%3Fwapkw=Error%2010515