Why does the F-Tile FHT transceiver design fail in the “Support Logic Generation” phase when the “Select FHT Lane PLL refclk source” parameter is set to "REF_TO_GND" as default? - Why does the F-Tile FHT transceiver design fail in the “Support Logic Generation” phase when the “Select FHT Lane PLL refclk source” parameter is set to "REF_TO_GND" as default? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, you might see failure in the “Support Logic Generation” phase when the Select FHT Lane PLL refclk source parameter is set to REF_TO_GND as default. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 23.2, select FHT Lane PLL refclk source to either PLL_100_MHZ or PLL_156_MHZ . Custom Fields values: ['novalue'] Troubleshooting 14016453661 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 22.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']