Why do I see long refresh cycles when using DDR3 SDRAM Controller with UniPHY in Stratix V devices? - Why do I see long refresh cycles when using DDR3 SDRAM Controller with UniPHY in Stratix V devices? Description You will see long refresh times both in hardware and in simulation when using UniPHY based DDR3 SDRAM controller IP in Stratix® V devices if the "Enable read DQS Tracking" feature is enabled. Enabling read DQS tracking is recommended when the memory clock frequency is 533MHz and above. When DQS tracking is enabled, the controller will be stalled after the refresh cycle (tRFC is met) and interface control will be passed to the sequencer. The sequencer will then perform read routines (Activate-Read-Precharge) to capture the DQS tracking information. The DQS tracking is performed everytime the controller completes a refresh, h ence the refresh time taken by the controller can appear to be longer than necessary. If "Enable Read DQS tracking" is disabled, refresh times will continue to conform to memory requirements. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0.1 ['Stratix® V E FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']