Why does the F-Tile JESD204C Altera® IP Design Example fail to compile when migrated from a previous version of the Quartus® Prime Pro Edition Software to version 24.3? - Why does the F-Tile JESD204C Altera® IP Design Example fail to compile when migrated from a previous version of the Quartus® Prime Pro Edition Software to version 24.3? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile JESD204C Altera® IP Design Example will fail to compile when migrated from any previous version of the Quartus® Prime Pro Edition Software to version 24.3. Resolution Follow the instructions below to work around this problem in the Quartus® Prime Pro Edition Software version 24.3 by manually editing the module to remove the unused port. In the Files tab under Project Navigator window, locate the ed_control IP file (…rtl/<data_path>/ip/j204c_f_<data path>_ss/j204c_f_<data path>_ss_ed_control.ip) . Expand the directory and find the target module (…rtl/<data_path>/ip/j204c_f_<data path>_ss/j204c_f_<data path>_ss_ed_control/synth/j204c_f_<data path>_ss_ed_control.v) Comment out the all “ csr_tst_ctl_tst_control_error_inject ” ports. For example : // output wire csr_tst_ctl_tst_control_error_inject This problem will be fixed in a future version of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15016926144 False ['F-Tile JESD204C IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.3 ['Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['novalue']