Timing Not Met in Stratix V Devices - Timing Not Met in Stratix V Devices
Description Multi-port Triple-Speed Ethernet MegaCore function designs that target Stratix V devices may not meet timing requirements. This issue affects multi-port Triple Speed Ethernet MegaCore function designs that target Stratix V devices. Resolution No workaround.This issue will be fixed in a future version of the Triple-Speed Ethernet MegaCore function.
Custom Fields values:
['novalue']
Troubleshooting
novalue
True
['Ethernet']
['FPGA Dev Tools Quartus II Software']
novalue
11.0
['Stratix® V FPGAs']
['novalue']
['novalue']
['novalue'] - 2021-08-25
external_document