Why is afi_rlat tied to ground in my UniPHY-based PHY-Only instance of the external memory interface? - Why is afi_rlat tied to ground in my UniPHY-based PHY-Only instance of the external memory interface? Description The use of the afi_rlat signal is not supported for PHY-Only designs. Resolution The workaround is to use the afi_rdata_valid signal to determine when valid read data is available. For more information, refer to the External Memory Interface Handbook . Custom Fields values: ['novalue'] Troubleshooting 1408188739 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']