Stratix 10 HPS 8GB SODIMM shared memory for HPS and FPGA - Stratix 10 HPS 8GB SODIMM shared memory for HPS and FPGA We have custom board with stratix 10 FPGA. the HPS boots from 8GB eMMC and teh linux runs of 2GB soldered DDR4. We also have a 8GB DDR4 SODIMM which we plan to use as a shared memory between the HPS and FPGA. We need help in interfacing this memory with the HPS and FPGA. There are about 8 FPGA modules that need to access the SODIMM along with teh HPS. So total of 8 ports to the memory controller. Can you suggest a solution for this. Is there any muti port wrapper ip for the EMI IP which we can use for this. Also, can the HPS h2f bridge access 8GB memory? Replies: Re: Stratix 10 HPS 8GB SODIMM shared memory for HPS and FPGA Hi Sajeev_antony , Do you have any feedback or other questions on this topic? Regards, AK Replies: Re: Stratix 10 HPS 8GB SODIMM shared memory for HPS and FPGA Hi Sajeev_antony , Typically, you would let Platform Designer generate the arbitration logic for EMIF with multiple Avalon-MM/AXI masters, or design a custom logic if the generated one doesn't match your needs - we don't offer a Multi-Port Front-End wrapper for Stratix 10 EMIF. You can then connect the HPS h2f bridge to the same conduit as the other masters. The HPS-to-FPGA bridge provides access to 4GB of address space: https://docs.altera.com/r/docs/683222/25.3.1/stratix-10-hard-processor-system-technical-reference-manual/hps-to-fpga-bridge For access to the full 8GB SODIMM, you would need an Address Span Extender IP to access the entire 8GB: https://docs.altera.com/r/docs/683364/18.1/intel-quartus-prime-standard-edition-user-guide-platform-designer/address-span-extender You should consider the bandwidth and latency needs for each master that needs access to the EMIF, and optimize accordingly. Regards, AK