What is the simulation behavior for rx_phase_comp_fifo_error when there is a difference between the read and write clock frequencies in Cyclone® IV GX devices? - What is the simulation behavior for rx_phase_comp_fifo_error when there is a difference between the read and write clock frequencies in Cyclone® IV GX devices? Description In the simulation, the rx_phase_comp_fifo_error signal for Cyclone® IV GX devices will assert when there is a difference in frequency between the read and write clocks of the phase compensation FIFO. Once asserted, rx_phase_comp_fifo_error will remain asserted until rx_digital_reset is asserted. However, if the read clock does not toggle in the simulation test bench, the rx_phase_comp_fifo_error signal will not assert. This does not match actual device behavior where rx_phase_comp_fifo_error will assert if the read clock is not toggling. Resolution N/A Custom Fields values: ['novalue'] Troubleshooting - False ['novalue'] ['novalue'] novalue novalue ['Cyclone® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']