Why do I see PTP failure due to accuracy error exceeding 3ns in Basic PTP Timestamp Accuracy Mode on F-Tile Ethernet Hard IP when dynamically reconfiguring from 100G-4 PTP to 4x25G PTP without FEC on hardware using example design from the F-Tile Suite? - Why do I see PTP failure due to accuracy error exceeding 3ns in Basic PTP Timestamp Accuracy Mode on F-Tile Ethernet Hard IP when dynamically reconfiguring from 100G-4 PTP to 4x25G PTP without FEC on hardware using example design from the F-Tile Suite? Description Due to a problem in the F-Tile Dynamic Reconfiguration Suite IP Example Design in Quartus® Prime Pro Edition software version 25.1.1, you may see PTP failed because it’s not meeting PTP accuracy requirement of 3ns for Basic PTP Accuracy mode in F-Tile Dynamic Reconfiguration Suite IP Available Example Design, when you will select the two options from GUI under Available Example Designs Tab 1) Select protocol/mode Ethernet and 2) Select base variant 100G-4 PTP in Table 10 of section 3.1.2 . The F-Tile Dynamic Reconfiguration Suite IP Available Example Design for 100G-4 PTP to 4x25G PTP with no FEC implementation is not meeting the specification provided in F-Tile Ethernet Hard IP User Guide in 25.1.1, causing the below PTP accuracy error for 4x25G PTP with no FEC. Other configurations in the same example design are not unaffected. Below is the snapshot of the PTP failure log output of TCL scripts run for example design when the PTP accuracy is missed by 66.4ps. Comparison #1 ------------------------------ RX_ITS - TX_ETS : 0x31100/3.0664 ns TX Timestamp Fields : 0x3031323334353637BBCC RX Timestamp Fields : 0x3031323334353637BBCC TX Correction Fields : 0x16AA18191A1B1C1D RX Correction Fields : 0x16AA18191A1B1C1D ERROR: PTP Failed As per recommendations provided in F-Tile Ethernet Hard IP User Guide under section 4.4.2 , separate TOD clocking is required for multiple 25GE/100GE Ethernet IP instances, and multiple 10GE Ethernet IP instances share a single TOD clock output. The Available Example Design for 100G-4 PTP does not follow the above recommendations and using single TOD for multiple instances of 25GE Ethernet IP causes accuracy error in default Basic Timestamp accuracy mode. Resolution To work around this problem, some changes are required in the F-Tile Dynamic Reconfiguration Suite IP Available Example Design for 100G-4 PTP in Figure 19, section 3.1.2 , to fulfill the requirement to achieve the expected accuracy as described in the F-Tile Ethernet Hard IP User Guide section 4.4.2 , Figure 16. Blue and brown curly lines in the figure below demonstrate the recommended TOD clock connections to fix the current PTP Failure in Basic PTP Timestamp Accuracy mode. The TOD clock source should be 390.625MHz. In the recommended flow for 25G to 400G rates, we are using the o_tx_clk_div clock coming out of the F-Tile Ethernet Hard IP, and due to this clock connection, separate TOD synchronizers and TOD slaves are required per instance. The required code changes in the two top-level RTL files of the example design that instantiate underlying IPs are also provided for reference 1) <DR 100G PTP Example Design Path>/hardware_test_design/eth_f_hw.v 2) <DR 100G PTP Example Design Path>/hardware_test_design/common/eth_f_hw_ip_top_100g.sv This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 14025726242, 14025661625 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']