Why am I seeing readback data corruption on my AXI-Lite client interface with the F-tile variant of the Ethernet Subsystem Intel® FPGA IP? - Why am I seeing readback data corruption on my AXI-Lite client interface with the F-tile variant of the Ethernet Subsystem Intel® FPGA IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, readback data corruption on the AXI-Lite client interface with the F-tile variant of the Ethernet Subsystem Intel® FPGA IP will occur if the AXI-Lite read transaction is in progress when subsystem_cold_rst_n is asserted. In this event, the first data being read back from the underlying Ethernet hard IP will be invalid. Resolution To work around this problem, if subsystem_cold_rst_n is asserted during an AXI_lite read transaction to the underlying Ethernet hard IP, you should ignore the readback data of the first read transaction and perform an additional read to the same location to obtain the proper readback data value. Custom Fields values: ['novalue'] Troubleshooting 16019995960 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']