Why does U-Boot fail to boot from SD Card in SD High-Speed mode in Agilex® 5 and Agilex® 3 FPGA production devices when the SOFT PHY clock is different than 200 MHz in release 26.1? - Why does U-Boot fail to boot from SD Card in SD High-Speed mode in Agilex® 5 and Agilex® 3 FPGA production devices when the SOFT PHY clock is different than 200 MHz in release 26.1? Description Due to the default SD Combo Phy timing parameters assigned in the U-Boot device tree ( socfpga_agilex5_socdk-u-boot.dtsi , socfpga_agilex5_socdk_013b-u-boot.dtsi ) for release 26.1, U-Boot may fail to boot from the SD Card in SD-HS mode on Agilex® 5 and Agilex® 3 FPGA production devices when the SOFT PHY clock is not 200 MHz (i.e. using 50 MHz). The problem lies in the fact that those default parameters are calculated using a soft PHY clock default value of 200 MHz, but the required timing parameters may differ for any other frequencies. This problem is observed mainly when the U-Boot FSBL fails to load the u-boot.itb from the SD Card, but it may also be observed when U-Boot SSBL fails to load Linux* from the SD Card. Resolution To workaround this problem, you need to enable a tuning mechanism from within the Cadence SDHCI driver by applying the attached U-Boot patch ( enable_hs_tuning.patch ). This tuning mechanism consists of a runtime calibration process to find the optimal data sampling point. The conditions in which this mechanism is active are: The boot device is a SD Card (no eMMC) The operation mode is SD-HS cdns,sd-hs-tuning parameter is enabled in the device tree The CONFIG_MMC_SUPPORTS_TUNING config is enabled The attached enable_hs_tuning.patch lists the updates needed to enable the tuning mechanism for a 50 MHz SOFT PHY clock. This is a temporary workaround that you could use until a proper software fix gets released. Note: The patch provided is for the Agilex® 5 DK-A5E013BM16AEA development kit (using socfpga_agilex5_socdk_013b-u-boot.dtsi ). For other Agilex® 5 or Agilex® 3 FPGA production development kits, the patch solution is the same, users are recommended to apply the updates to the respective device tree file ( i.e. socfpga_agilex5_socdk-u-boot.dtsi , socfpga_agilex3_socdk-u-boot.dtsi ). The source code to support the tuning mechanism will be included in a future release. Custom Fields values: ['novalue'] Troubleshooting ES-430 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 26.1 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 3 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']