Why does the Quartus II software reports minimum pulse width violations for the 40Gb/100Gb Ethernet MAC and PHY Example Design? - Why does the Quartus II software reports minimum pulse width violations for the 40Gb/100Gb Ethernet MAC and PHY Example Design? Description Due to a bug of the Quartus® II software version 12.0 and 12.0SP1, the minimum pulse width violations are reported. Resolution The minimum pulse width violations can be safely ignored with the Quartus II software version 12.0 and 12.0SP1. This issue is fixed in version 12.0SP1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0.2 12.0 ['Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']